The invention generally relates to silicon (Si) CMOS transistor technology and, more particularly to silicon-germanium-based techniques for modifying the Si technology to enhance the performance of the CMOS transistors, particularly the p-channel transistors.
U.S. Pat. No. 4,994,866, issued to Yuji Awano on Feb. 19, 1991 notes the prior art teachings that silicon is usually employed as the material for CMOS devices and that the switching speed of the silicon PMOSFET is slower than that of the silicon NMOSFET. Thus, the switching speed of the CMOS circuit as a whole is limited by that of the PMOSFET.
In order to increase the switching speed of the PMOS toward the level of that of the NMOS, it is proposed in the cited patent that increased hole mobility for the PMOS may be provided by growing on a silicon substrate, in sequence, a first layer of silicon-germanium (Si--Ge), a layer of Ge, a second layer of Si--Ge and a top layer of Si. Portions of the substrate containing PMOSFETS and NMOSFETS are isolated from each other by grooves extending from the top layer to the substrate. The channel layer of the PMOSFET comprises the aforementioned Ge layer. The channel layer of the NMOSFET comprises the aforementioned top Si layer.
Although the above described patent teaching is aimed at making the switching speed of the CMOS device limited by the Nchannel (Si) device of the proposed Si/Si--Ge CMOS, rather than by the Pchannel (Si) of the earlier-art all--Si CMOS, the described Si--Ge CMOS process does not use oxide isolation to isolate PMOS from NMOSFETS and otherwise does not bear close resemblance to preexisting, well-developed production CMOS processes.